In some memory architectures, a memory controller communicates with a memory module through a command/control (CMD/CTL) bus as well as a data bus. The fast signaling rates on the CMD/CTL bus drives the need for tight timing control between the CMD/CTL signals and the clock (CLK). In conventional systems, the relative spacing between the CMD/CTL signals and the CLK is statically programmed based on a combination of motherboard routing guidelines, system simulations, and empirical data.